Laser voltage imaging (LVI) and Laser voltage probing (LVP) are laser-based voltage and timing waveform acquisition techniques used to perform failure analysis on flip-chip integrated circuits (ICs) or to localize failures in ICs. The LVP tool CAD alignment process includes a coarse three point alignment at very low magnification using solid immersion lens (SIL). The SIL is a spring-loaded lens that makes direct contact with the backside of the silicon substrate of the IC for high resolution imaging (e.g., LVI, Laser Scanning Microscope (LSM) image). However, due to the spring nature of the SIL, the LSM image can be slightly off with respect to the CAD when the SIL first makes a contact with the silicon substrate or whenever the SIL shifts to a different location. In 10 nm and smaller IC technology, with the increasing density and decreasing feature sizes, the current electrical fault isolation (EFI) tools (e.g., LVP) are reaching the limit of image resolution, which consequently translates to problems with CAD-to-image alignment, since it becomes very hard to distinguish one feature from another. Therefore, there is a need for visible alignment markers in 10 nm and smaller IC technology for a precise local alignment during the LVP measurement of an IC for EFI to ensure that the correct standard cell or signal is being probed.